The present invention relates to a wiring layout technique for semiconductor memory devices, and more particularly to a technique effectively applicable to attempts at reducing parasitic capacitances formed between bit lines for reading signals out of memory cells and a signal transmission line arranged on a layer above them.
Japanese Unexamined Patent Publication No. Hei 7(1995)-58215 (corresponding U.S. Pat. No. 5,625,234) discloses a wiring method for dynamic random access memories (DRAMs) (method of arranging bit lines and Y select lines).
Usually, a DRAM uses a wiring system by which Y select lines for selecting column addresses are arranged on a layer above bit lines and extend in parallel to the bit lines. However, as this wiring system entails large parasitic capacitances between the Y select lines and the bit lines, any variation in potential on the Y select lines would work in an unbalanced way on bit line pairs (bit line/complement bit line), and might destabilize the sensing of stored information from memory cells.
In view of this problem, according to the above cited patent application, Y select lines are arranged at equal distances to bit line pairs to equalize the parasitic capacitances of the bit line pairs against the Y select lines and thereby to reduce the adverse effect on the bit lines. In this wiring structure, as parasitic capacitances between Y select lines and nearby bit line pairs are balanced, sensing of stored information from memory cells can be accomplished steadily and reliably. However, even where this wiring structure is used, there is an undeniable imbalance of parasitic capacitances for other bit lines adjoining the noted bit lines. Therefore, for such adjoining bit lines, the parasitic capacitances against Y select lines are substantially equalized by twisting the bit line pairs midway on the Y select lines. Regarding the configuration of bit lines, reference may be made to Japanese Unexamined Patent Publication No. Sho 64(1989)-14954, Japanese Unexamined Patent Publication No. Hei 10(1998)-289987 (corresponding U.S. Pat No. 6,088,283), Japanese Unexamined Patent Publication No. Hei 7(1995)-45722 and Japanese Unexamined Patent Publication No. Hei 5(1993)-218348 (corresponding U.S. Pat. No. 5,170,243 and U.S. Pat. No. 5,292,678).
The present inventor has studied a technique for reducing the chip area of static random access memories (SRAMs).
A SRAM amplifies with a sense amplifier circuit signals read out of memory cells through bit lines, and outputs them over a signal transmission line. Usually such a signal transmission line is arranged on the wiring channels of peripheral circuits and laid in a chip all around.
However, in order to compress the chip area of a SRAM to reduce its cost, it is required also to compress the area of wiring channels along with reducing the memory cell size infinitesimally. While a conceivable way to meet this requirement is to arrange a signal transmission line, which would otherwise be arranged on wiring channels, on a memory cell array, but if the signal transmission line is arranged over bit lines formed on the memory cell array, parasitic capacitances will be formed between the bit lines and the signal line extending in parallel to them.
From a SRAM, only a small amplitude is outputted on bit lines by the capacities of memory cells, and amplification by the sense amplifier results in no signal amplification on the bit lines. Therefore, if signal transmission wiring passes over bit lines on which the signal amplitude is always small, the timing of any variation in the signal level on this signal transmission line coincides with the activity of the bit lines, parasitic capacitances formed between the signal transmission line and the bit lines may adversely affect the bit lines and invite erroneous actions.
An object of the present invention is to provide a technique for reducing the chip area of semiconductor memory devices.
Another object of the invention is to provide a technique for reducing parasitic capacitances formed between bit lines for reading signals out of memory cells and a signal transmission line arranged in a layer above them.
These and other objects and novel features of the invention will become apparent from the following description in this specification when taken in conjunction with the accompanying drawings.
What follows is a brief summary of typical aspects of the invention disclosed in this application.
In a semiconductor memory device according to one aspect of the invention, a signal transmission line is arranged over a memory cell array. By laying out this arrangement so that a signal transmission line extending in a layer above a pair of complementary bit lines in parallel to the bit lines be at equal distances to the bit line and the complement bit line directly underneath them, the capacitance between the signal transmission line and the bit line can be substantially equalized to the capacitance between the signal transmission line and the complement bit line.
In a semiconductor memory device according to another aspect of the invention, by bending a signal transmission line above complementary bit lines near the center of the length of the complementary bit lines and arranging it over other complementary bit lines, other bit lines than the complementary bit lines directly underneath the signal transmission line can have capacitances substantially balanced with the signal transmission line.